CZT-firmware

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List of included modules in hierachical order:

Detector module interface (dm_if)

interface to readout electroncs for the detector modules. Reads energy, pixel and ASIC address, in addition to multihit information. Also controls the pipelined ADC.

Offset substract

Finds and subtracts the offset from ADC data, ensuring a consistent mean value of zero between all four detector chains

Hit discriminator (hit_dicr)

determines whether there was an event or not?

Memory bus interface (mb_if)

for communication with user interface. including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.

input:

  • memory address memadr_in (from adress decoder)
  • memory data memdat_in (from address decoder, incl. command )
  • status register sr[0-3] (from logic module, e.g. tmon)
  • clk etc.

output:

  • memdat_out (to address decoder, incl. answer)
  • control registers cr[0-3] (to logig module, incl. command)

MUX (scdp_ch_mux)

The chain multiplexer receives the SCDP from readout chains (one chain contains 8 ASICS, that are 1024 channel) and writes data into the FIFO

FIFO

DPU interface (dpu_if)

is interfacing the DPU emulator, input: commands, output: data, status

  • asim_common_lib
 port (
    clk               : in  std_logic;  -- clock
    arst_n            : in  std_logic;  -- asynchronous reset    
    memdat_in         : in  std_logic_vector(7 downto 0);  -- memory bus data input
    serial_data_in    : in  std_logic;  -- serial data input
    serial_strobe_in  : in  std_logic;  -- serial strobe input
    serial_data_out   : out std_logic;  -- serial data output
    serial_strobe_out : out std_logic;  -- serial strobe output
    RnW               : out std_logic;  -- read / write control
    ld_memdat         : out std_logic;  -- load memory data
    memadr_out        : out std_logic_vector(13 downto 0);  -- memory address
    memdat_out        : out std_logic_vector(7 downto 0);   -- memory data
    scdp              : in  std_logic_vector(47 downto 0);  -- scdp input
    enable            : in  std_logic;  -- enable input from DPU
    fifo_empty        : in  std_logic;  -- fifo empty indicator
    fifo_read         : out std_logic;  -- fifo read enable
    fifo_full         : in  std_logic := '0');  -- fifo full indicator


receiving:

xlink_rx

Description: receiver for "xlink", a serial data strobe encoded point to -- point communications protocol for the ASIM MXGS

rx register

reception register for DPU interface

transmission:

xlink_tx

fsm

tx register

transmission register for DPU interface

tx control fsm

Address decoder (adrdec_bgo)

memory bus address decoder and data multiplexor

  • decodes the memory_address_in (memadr_in) and delivers data to called modules
  • the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
  • delivers answer (memdat, memory data) from modules

modules in control/status chain:

  • detector module interfaces (4 -- one per chain)
  • XA configuration (4 -- one per chain)
  • RCU master
  • bin control

input:

  • memadr_in (from dpu_if/user)
  • memdat_out_[0-9] (from modules)
  • clk etc.

output:

  • memadr_out (to modules)
  • di_memdat_in (to dpu_if)

Binning control module (BCM) (bin_ctrl_module)

The BCM delivers status reports of the collected data. It generates a 2D table out of SCDP coming from the pmt_if. This table includes temporal and spectral bins. Time and energy value from the SCDP are analyzed and assigned to a temporal and spectral bin. That bin value then will be incremented. There are lower and higher boundaries for the spectral bin value. If the energy value in the SCDP is outside the boundaries it will be discarded. The spectral boundaries are configurable via the mb_if. The result also is delivered via mb_if.

Scdp channel mux

Bin address generator

Bin access control

Swing buffer

Bin module address arbiter

Memory bus interface (mb_if)

see mb_if in detector module interface

RCU master (rcumaster)

LED control

FSM

Memory bus interface (mb_if)

see mb_if in detector module interface

XA config (xa_cfg)

XA register verification (xa_reg_verify)

FSM, ASIC configuration register verifier

RAM (dpram1k8)

RAM to memorize control register, dual port RAM for volatile XA configuration data

Memory bus interface

see mb_if in detector module interface

piso8_ctrl

FSM

Resync register

synchronizes the inputs and outputs of the FPGA with the internal clock signal.

Clock reset (clkrst)

This module generates the clock and the reset signal for the firmware components. The signals are based on a crystal oscillator input and a global clock.

Timetag generation (tt_gen)

The time tag generator provides information about when an event happens. It maintains a 20-bit counter used to timestamp science events. The 20-bit time stamp then become part of the science data package (SCDP) .