DCS board tools

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Detector Control System

Overview

This sections covers the DCS board software for the TPC-like detectors (so far TPC, PHOS, most likely FMD and EMCAL). Apart from the mentioned FeeServer there are some low level tools and interfaces. In fact, the FeeServer uses them.


File:DCSboard software components.png
DCS board Software Components


The DCS board communicates via two interfaces to the RCU board:

  1. The Message Buffer Interface: used for most of the data tranfer between software and memory on the RCU
  2. The Direct Bus Access: programming of RCU Flash Memory and FPGA Configuration Memory

A driver (rcubus_driver) provides the access to the interfaces via the following devices. A C-interface (RCU interface) implements basic functionality for the Message Buffer Interface. It is used by both the RCU shell (low level tool) and the FeeServer

Access to the RCU

The figure illustrates the the available hardware interfaces: Message Buffer Interface and Direct Bus Access.

File:DCSboard-RCU interface.png
Hardware interfaces between DCS board and RCU

The data flow is controlled by lines in the Control Register:

  • Bit 7 Start Command
  • Bit 6 MIB multiplexer, read enable
  • Bit 0 Ready
  • Bit 5 Direct mode select

The idea behind the Message Buffer Interface:

  • the interface moves some of the complexity to the firmware
  • decouples cpu from the communication task
  • block by block transfer
  • 2 Buffers for communication and one Control Register
    • Message Input Buffer (MIB)
    • Message Result Buffer (MRB)
    • Control Register
  • basic sequence from software view
    • write command sequence to MIB
    • set 'execute' flag
    • wait for the 'ready' flag
    • read result and status

In Direct Bus Access mode the driver (or a specific subdriver) takes control over the bus lines.

RCU bus driver

The following devices are available resp. are planned to be that:

  • /dev/rcu/msgbuf message buffer interface
  • /dev/rcu/fpga fpga configuration (under development)
  • /dev/rcu/flash general flash memory access (under development)
  • /dev/rcu/flash0 flash memory bank 0 (under development)
  • /dev/rcu/flash1 flash memory bank 1 (under development)
  • /dev/rcu/flash2 flash memory bank 2 (under development)
  • /dev/rcu/flash3 flash memory bank 3 (under development)

Message Buffer access (RCU interface)

The Message Buffer interface is a memory mapped interface. A certain command sequence has to be written to the Message Input Buffer (MIB).

A command sequence constists of a 32-bit header word, the command words and a 32-bit marker word which terminates one sequence block. Several sequence blocks can be grouped and are finally terminated by the End marker word. The structure is outlined in the following figure.

File:MsgBufferFormat.png
Format of the Message Buffer input


Command ids

  • Bit 5-0 of the header word
Command Name Command Code Description Command words # command words
SINGLE_READ 0x1 a single read operation
address
1
SINGLE_WRITE 0x2 a single write operation
address
data
2
MULTI_READ 0x3 block read operation
The count parameter indicates the number of words of a certain format
(see control bits)
address
count
2
MULT_WRITE 0x4 block write operation
The count parameter indicates the number of words of a certain format
(see control bits)
address
count
data #1
...
data #n
2 + # data words
RANDOM_READ 0x5 random read operation
address #1
address #2
...
address #n
number of addresses
RANDOM_WRITE 0x6 random write operation
address #1
data #1
address #2
data #2
...
address #n
data #n
2 x number of addresses
FLASH_ERASEALL 0x21 erase the flash completely
0


FLASH_ERASE_SEC 0x22 erase one sector of the flash
address
1


FLASH_MULTI_ERASE 0x24 erase multiple sectors of the flash
address
count
2


FLASH_READID 0x28 read the ID of the flash
0 = Manufacturer ID / 1 = Device ID
'0' or '1'
1
FLASH_RESET 0x30 reset the flash
0

Word count

  • Bit 15-6 of the header word
    must contain the number of words between the Header end the Marker.

Block number

  • Bit 23-16 of the header word
    number of the current sequence block
    The first block has number n-1, the block number is decremented for the following blocks. The last block has block no 0. If there is only one sequence block, the block no bits are just zero.

Control bits and block number

  • Bits 25-24 Data Format
25 - 25 Description Data Format
0 0 no compression
31 0
address
0 1 2 x 16 bit words
31 16 15 0
address + 1 address
1 0 3 x 10 bit words
29 20 19 10 9 0
address + 2 address + 1 address
1 1 4 x 8 bit words
31 24 23 16 15 8 7 0
address + 3 address + 2 address + 1 address

Version

  • Bit 31 - 28 of header word
    version of Message Buffer specification
31 - 28
0 x x x version 1 (bit 31==0, other bits arbitrary)
1 0 1 0 version 2
1 0 1 1 version 2.2
1 1 1 1 FeeServer command (used outside the message buffer interface)

Result Format

Word # Description


1
31 16 15 0
Number of words
Information Word


2
31 0
Status word
3 - n
31 0
Data
Status word:
0 - if no error
Bit 15 set if any error

Bit 0: missing marker
Bit 1: missing end marker
Bit 2: no target answer (something wrong with the RCU or not connected)
Bit 3: no bus grant (no access to the bus on dcs board)
Bit 5: old message buffer format (prior to v2 with rcu-sh version v1.0)

Examples

Single read

from address 0x7000

0xA0000041 Information word
0x00007000 address 0x7000
0xAA550000 Block marker without Checksum
0xDD330000 End marker

Multiple write

4 words starting at address 0x6800

0xA0000184 Information word
0x00006800 address 0x6800
0x00000004 4 words to write
0x0000AFFE data word 1
0x0000D00F data word 2
0x00001234 data word 3
0x00005678 data word 4
0xAA550000 Block marker without Checksum
0xDD330000 End marker

Multiple write with 3x10 bit compress

3x3 10bit words starting at address 0x7000 and finishing at 0x7008

0xA2000144 Information word
0x00007000 address 0x6800
0x00000003 4 words to write
0x2A995566 data word 1
0x1EADBEEF data word 2
0x01020202 data word 3
0xAA550000 Block marker without Checksum
0xDD330000 End marker


Flash Erase all

Erasing the complete content on the RCU Flash Memory

0xA4000021 Information word
0xAA550000 Block marker without Checksum
0xDD330000 End marker

Flash Erase Multiple Sectors

Erasing multiple subsequent sectors on the RCU Flash Memory

0xA40000E4 Information word
0x003E8000 Address of first sector (Word Address)
0x00000004 Number of sectors to Erase
0xAA550000 Block marker without Checksum
0xDD330000 End marker

RCU shell

The RCU Shell is a small command-line software for communcating with the firmware on the RCU motherboard. It is started by simply typing 'rcu-sh' at the command-line. This will bring you to the shell mode, where different types of commands can be executed.

The RCU motherboard can be operated in three different modes.

  1. Memory mapped mode
  2. Selectmap mode
  3. Flash mode

The default mode is memorymapped mode, which gives you direct memory access of the registers in the FPGAs on the RCU motherboard.

Flash mode gives the dcs board direct control of the flash memory on the RCU motherboard, while selectmap mode gives the dcs board direct control over the selectmap interface of the Xilinx Virtex-II on the RCU motherboard.


Memory mapped mode

Selectmap mode

The Selectmap mode is enabled by typing:

enter operation (h/i/q/r/w): selectmap enable

or

enter operation (h/i/q/r/w): sm e

The following options is available: 1. Get help on commands:

sm help

2. write to single address via the selectmap interface:

sm w 0x[address] 0x[data]

3. read from single address via the selectmap interface:

sm r 0x[address]

4. Abort ongoing operation on the Xilinx FPGA:

sm abort

Flash mode

The flash mode is enabled by typing:

enter operation (h/i/q/r/w): flash enable

The following options is available:
1. Get help on commands:

flash help

2. Write to single address in flash:

flash write 0x[address] 0x[data] [num]
num = number of sequental addresses to write the given data to

3. Write a file from a start address in the flash:

flash write [-s] 0x[address] file [size]
-s = byteswap enabled
size = number of 16 bit words to write to the flash from beginning of file.

4. Erase complete flash:

flash erase all

5. Erase sector:

flash erase sec 0x[sector address]

6. Read single address from flash:

flash read 0x[address] [num]
num = number of sequental address to read from the given address. 

7 Verify content of the flash memory:

flash verify 0x[address] file
Verifies that the content of the flash from the given address matches the content of the given file.

Connection to FeeServer

File:DCSboard TPC-ControlEngine connection.png
Connection of the FeeServer Control Engine (TPC version) to the Hardware interfaces