User contributions
- 11:50, 6 November 2018 (diff | hist) . . (+49) . . m TSMC 130nm process (Added if IHP are used, use SG13_dev technology) (current)
- 17:47, 4 May 2018 (diff | hist) . . (+2,472) . . Layout XL and IHP SG13S (Added Parasitic extraction QRC and Post Layout Simulation)
- 17:28, 4 May 2018 (diff | hist) . . (0) . . N File:Hierarchy editor.png (current)
- 17:00, 4 May 2018 (diff | hist) . . (0) . . N File:LVS summary.png (current)
- 13:43, 4 May 2018 (diff | hist) . . (0) . . N File:Extracted layout SRAM with bt wd.png (current)
- 10:52, 3 May 2018 (diff | hist) . . (0) . . N File:ASSURA QRC.png (current)
- 19:17, 21 April 2018 (diff | hist) . . (+112) . . m MikroserverSetup (Added command for copying folders)
- 19:01, 21 April 2018 (diff | hist) . . (+530) . . Cadence Testbench (Added simulation procedure) (current)
- 15:33, 11 April 2018 (diff | hist) . . (+2) . . m TSMC 130nm process
- 13:46, 11 April 2018 (diff | hist) . . (-5) . . m TSMC 130nm process (Moved launch ade gxl from entering to simulation)
- 14:38, 13 March 2018 (diff | hist) . . (+144) . . m Modelsim/Questa (Updated a dead link)
- 16:14, 12 March 2018 (diff | hist) . . (+103) . . m Synthese av VHDL - Oppdatert (Link til intel si nedlastingsside for quartus og modelsim) (current)
- 13:49, 12 March 2018 (diff | hist) . . (+264) . . m XJTAG (Updated path to XJTAG 3.5)
- 15:18, 8 March 2018 (diff | hist) . . (+45) . . m Bitvis UVVM VHDL Verification Component Framework (Corrected write and read signal names in set_inputs_passive and fixed dead link)
