Gallery of new files

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This special page shows the last uploaded files.

Puttyx11.png Bhu006
14:22, 3 May 2020
17 KB
Puttylogin.png Bhu006
14:22, 3 May 2020
22 KB
SG13 Layout rules.pdf Bhu006
11:37, 27 April 2020
921 KB
SG13 Design Kit User Guide.pdf Bhu006
11:37, 27 April 2020
2.07 MB
Hierarket.jpg Gge002
15:29, 29 May 2018
638 KB
Hierarchy editor.png Put009
17:28, 4 May 2018
78 KB
LVS summary.png Put009
17:00, 4 May 2018
30 KB
Extracted layout SRAM with bt wd.png Put009
13:43, 4 May 2018
120 KB
ASSURA QRC.png Put009
10:52, 3 May 2018
108 KB
Shaper.ps.jpg Fli091
16:24, 22 March 2018
22 KB
CadencePlotOptions.png Fli091
15:46, 22 March 2018
44 KB
CadencePrintWindow.png Fli091
15:45, 22 March 2018
51 KB
Running concurrent xilinx sdk added.png Yag005
17:17, 4 January 2018
72 KB
Running concurrent xilinx sdk not added.png Yag005
17:08, 4 January 2018
140 KB
Fsbl created.png Yag005
19:53, 6 December 2017
15 KB
Project explorer start.png Yag005
19:49, 6 December 2017
13 KB
Main code.png Yag005
19:35, 6 December 2017
53 KB
AXILedBlink code.png Yag005
19:32, 6 December 2017
26 KB
Remove include demo libs.png Yag005
19:23, 6 December 2017
45 KB
Source folder.png Yag005
19:05, 6 December 2017
118 KB
FreeRTOSConfig cpu freq edit.png Yag005
17:51, 6 December 2017
192 KB
Port c edit.png Yag005
17:46, 6 December 2017
246 KB
Lscript id edit.png Yag005
17:39, 6 December 2017
134 KB
Led port success.png Yag005
18:52, 4 December 2017
24 KB
S00 1.png Yag005
18:49, 4 December 2017
90 KB
S00 2.png Yag005
18:48, 4 December 2017
82 KB
Led ip 1.png Yag005
18:48, 4 December 2017
85 KB
Led ip 2.png Yag005
18:48, 4 December 2017
94 KB
Led ip 3.png Yag005
18:48, 4 December 2017
75 KB
Diagram axi4lite periph added.png Yag005
16:24, 4 December 2017
68 KB
Add interfaces axi4lite.png Yag005
15:44, 4 December 2017
29 KB
First block.png Yag005
16:43, 28 November 2017
35 KB
Create block design.png Yag005
16:33, 28 November 2017
16 KB
New project default part.png Yag005
16:25, 28 November 2017
41 KB
New project name.png Yag005
16:01, 28 November 2017
24 KB
Export hardware.png Yag005
15:46, 28 November 2017
12 KB
Launch SDK.png Yag005
15:42, 28 November 2017
13 KB
Geometry hiarerachy.png Hpe090
10:55, 24 November 2017
14 KB
Root file hierarchy.PNG Hpe090
10:55, 24 November 2017
32 KB
Root.PNG Hpe090
10:55, 24 November 2017
39 KB
Root2.PNG Hpe090
10:55, 24 November 2017
43 KB
Ranges.PNG Hpe090
10:55, 24 November 2017
34 KB
HEPP-2017-report-not-final.pdf Nfyal
22:46, 20 November 2017
4.68 MB
AnnotationSetupWindow.png Fli091
17:54, 11 November 2017
92 KB
AnnotationMenu.png Fli091
17:53, 11 November 2017
65 KB
PmosWithDCParameters.png Fli091
17:51, 11 November 2017
10 KB
ConnectToServer.png Fli091
12:41, 31 October 2017
6 KB
Manual CRT.pdf Nfyal
12:29, 17 October 2017
2.76 MB
2hdmML.pdf Nfyal
05:05, 23 September 2017
679 KB
MasterAssignment-Are.pdf Nfyst
12:32, 18 September 2017
24.46 MB

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