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* ''''ADC_setTriggerMode'''' Sets internal/external/random trigger signal and edge. ...'''' Sets the window position in relation to the trigger (0-127, 64 equals trigger in centre).

- Local trigger unit (LTU) - Switching to LTU trigger

Here you will find informations around the developing of the HLT (High Level Trigger) for [http://aliceinfo.cern.ch/index.html ALICE], especially for the [http:

| Number of pre-samples (Pretrigger delay), max 191 | Trigger count

...lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control. diff_trig : in std_logic; -- differential trigger

| Event trigger | Heartbeat trigger

...usyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module. ....e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.

|rowspan="3"|The EventID most recently received from the Trigger system. |L1 Trigger Timeout(15:0)

...es use the geometry definition <tt>ATLAS-CSC-01-02-00</tt> and the DEFAULT trigger. Remember that the '''Geant4''' step is very slow, run in a few events only #[ <tt>triggerConfig</tt> ] (str) default='DEFAULT'

4. Add this trigger: Trigger at 50% of trace

'''Trigger''' bool L1_J55; ''Level 1 Jet trigger (jet energy>55 GeV ?)

...the motors are uneven, and the detectors have to be kept in the dark when triggered the coordinates of the pixels has to be mapped out and stored. The motor ...rator should be set to send a step signal as the fast LED pulser will then trigger the attached LED on its falling edge. The amount of light emitted depends o

...verting, hak av for find closest reference edge og trykk apply. Skift edge trigger til nedadgående og trykk apply igjen.

...2.6uib when logging in, if intended to use together with the RCU. For the Trigger OR and the BusyBox a special firmware has been made. This firmware is avail '''2.61 Trigger-OR'''<br>

...find the Spartan U1 and virtex chipscope interfaces, by setting up proper trigger conditions we could get the waveform of all the signals we want. ...d" signal of all pattern match signals from the chips being enabled. If we trigger with "fram_sync_int", which is the signal for the start of the last line in

| on || RCU_TRCFG || trigger configuration and status || 0.5 || 32 || hex || -- | on || RCU_CNT || trigger count || 0.5 || 32 || hex || --

*TRIGGERCONFIGURATION1 *TRIGGERCONFIGURATION2

echo '<fee>CE_TRIGGER_TRANSITION ACTEL switchon</fee>' | feeserver-ctrl --server TPC-FEE_0_13_1 echo '<fee>CE_TRIGGER_TRANSITION ACTEL GO_Scrubbing</fee>' | feeserver-ctrl --server TPC-FEE_0_13

...board, which is used for clock generation and synchronization, data FIFO, trigger FIFO, 16 Mbytes board SRAM support module level histogramming, FPGA for enc ...se of 3D pixel single chip used, unchanged “PCC/PICT”, “Strobe setup” and “Trigger setup” values. Then select F for the “Global Address” (GA) and fill a

With a higher electric field, a situation is created, in which one avalanche trigger itself a second avalanche at a different position. The difference between both modes relies on the holes: in Geiger mode, they trigger avalanches, whereas in proportional mode they have not enough energy to do