Difference between revisions of "BGO-firmware-structure"

Line 45: Line 45:
Memory bus interface.  
Memory bus interface.  
including a control register and a fsm. basically a translator.  
including a control register and a fsm. basically a translator.  
translating memory data into commands for active module and delivers status reports.
translating memory data into commands for active module and delivers status reports.

Revision as of 15:37, 13 October 2010

BGO channel (bgo_channel_[0-2])

There are 3 BGO channels, each interfacing one PMT. Each BGO channel is hosting an own FIFO to store the event data. The readout of the fifos is controlled by the MUX block.

PMT interface

PMT = photo multiplyer tube

Taks: collects the ADC data from the detector, creates science data packets (SCDP) ans stores the data in a fifo. tasks included: lowpass filter, offset correction, tail estimation, shaping, peak detect, trigger & control.

  • mxgs_bgo_lib
  • 2009 by yngve (auto)

included blocks:


is a fsm

port (
      arst_n       : in  std_logic;     -- asynchronous reset
      rst          : in  std_logic;     -- synchronous reset
      clk          : in  std_logic;
      diff_trig    : in  std_logic;     -- differential trigger
      ovf          : in  std_logic;     -- ADC overflow
      peak         : in  std_logic;     -- peak found
      val_trig     : in  std_logic;     -- value trigger
      fast         : in  std_logic;     -- pulse ocurred on the tail of another pulse
      offset_lock  : in  std_logic;     -- offset is found
      load         : out std_logic;     -- load scdp
      offset_en    : out std_logic;     -- offset enable
      acc_en       : in  std_logic;     -- baseline correction enable
      hug          : out std_logic;     -- release the peak hold register
      par_clr      : out std_logic;     -- clear paralyzation flag
      inhibit      : in  std_logic;     -- inhibit further triggers
      smalltrig_en : in  std_logic;     -- enable small triggers
      adc_en       : out std_logic;     -- ADC enable
      smpl_mode    : in  std_logic;     -- direct sampling mode
      fifo_full    : in  std_logic;     -- fifo full flag
      fifo_empty   : in  std_logic;     -- fifo empty flag
      smpl_trig    : out std_logic      -- feedthrough of ADC data to FIFO


Memory bus interface. including a control register and a fsm. basically a translator.

translating memory data into commands for active module and delivers status reports.


  • memory address memadr_in (from adress decoder)
  • memory data memdat_in (from address decoder, incl. command )
  • status register sr[0-3] (from logic module, e.g. tmon)
  • clk etc.


  • memdat_out (to address decoder, incl. answer)
  • control registers cr[0-3] (to logig module, incl. command)


  • asim_common_lib
  • by yngve 2008

mov_avrg and mov_avrg8

moving avarage.

is a type of finite impulse response filter used to analyze a set of data points by creating a series of averages of different subsets of the full data set. (http://en.wikipedia.org/wiki/Moving_average)


pulse tail cancellation in order to reduction of systems dead time. several filters.

two separate tail estimation filters are used to enable tail cancellation of several consecutive pule tails. they will be used alternately, outputs are summed.

find document "BGO extention" written by yngve for further details.


is a fsm. selcting a trigger? output= 'tg_sel' being 0 or 1


stores SCDP per channel


  • mxgs_bgo_lib

MUX (bgo_mux)

coordinates data which should be read out from fifos. ... interface to the 3 fifos included in BGO_channels

  • mxgs_bgo_lib
  • 2010 by magne (auto)

        arst_n      : in     std_logic;                         -- asynchronous reset
        clk         : in     std_logic;                         -- clock
        fifo_read   : in     std_logic;                         -- read fifo from current chain
        data_na     : out    std_logic;                         -- data not available
        ch1_data    : in     std_logic_vector ( 47 downto 0 );  -- scdp from chain 1
        ch2_data    : in     std_logic_vector ( 47 downto 0 );  -- scdp from chain 2
        ch3_data    : in     std_logic_vector ( 47 downto 0 );  -- scdp from chain 3
        dout        : out    std_logic_vector ( 47 downto 0 );  -- arbitrated data
        sfifo_empty : in     std_logic_vector (1 to 3);
        sfifo_read  : out    std_logic_vector (1 to 3)

Address decoder (adrdec_bgo)

memory bus address decoder and data multiplexor

  • decodes the memory_address_in (memadr_in) and delivers data to called modules (pm_if_0, pm_if_1, pm_if_2, tmon or binctrl)
  • the module_base address (e.g. tmon_base) is defined in the mxgs_bgo_pk package.
  • delivers answer (memdat, memory data) from modules


  • memadr_in (from dpu_if/user)
  • memdat_out_[0-4] (from modules)
  • clk etc.


  • memadr_out (to modules)
  • di_memdat_in (to dpu_if)


  • mxgs_bgo_lib
  • 2008 by yngve

Binning control module (BCM) (bin_ctrl_module)

the BCM generates a 2D table out of SCDP coming from the pmt_if. the table includes temporal and spectral bins. time and energy value from the SCDP are analysed and assigned to a temporal and spectral bin. that binvalue then will be incremented.

there are lower and higher bondaries for the spectral bin value. if the energy value in the SCDP is outside that boundaries it will be discarded. the spectral boundaries are configurable via the mb_if. -> some kind of filter

  • asim_common_lib

included modules:

scdp channel mux

bin address generator

bin access control

swing buffer

bin module address arbiter

memory bus interface

DPU interface (dpu_if)

is interfacing the DPU emulator, input: commands, output: data, status

  • asim_common_lib
 port (
    clk               : in  std_logic;  -- clock
    arst_n            : in  std_logic;  -- asynchronous reset    
    memdat_in         : in  std_logic_vector(7 downto 0);  -- memory bus data input
    serial_data_in    : in  std_logic;  -- serial data input
    serial_strobe_in  : in  std_logic;  -- serial strobe input
    serial_data_out   : out std_logic;  -- serial data output
    serial_strobe_out : out std_logic;  -- serial strobe output
    RnW               : out std_logic;  -- read / write control
    ld_memdat         : out std_logic;  -- load memory data
    memadr_out        : out std_logic_vector(13 downto 0);  -- memory address
    memdat_out        : out std_logic_vector(7 downto 0);   -- memory data
    scdp              : in  std_logic_vector(47 downto 0);  -- scdp input
    enable            : in  std_logic;  -- enable input from DPU
    fifo_empty        : in  std_logic;  -- fifo empty indicator
    fifo_read         : out std_logic;  -- fifo read enable
    fifo_full         : in  std_logic := '0');  -- fifo full indicator



Description: receiver for "xlink", a serial data strobe encoded point to -- point communications protocol for the ASIM MXGS

rx register

reception register for DPU interface




tx register

transmission register for DPU interface

tx control fsm

Temperature monitor (tmon_struct)

used for temperature compensation and housekeeping controls external MUX and a ADC.

temperature monitor

General description : This module is designed to control an analog mux and an ADC to capture values from three different analog sources, in this case termistor values for temperature meseurements.

This module connects to the standard internal bus interface in the CZT/BGO firmware. It controls an external analog MUX and an ADC to sample three analog values representing temperatures. when the ADC data in a channel passes a certain limit an alarm is set. the limit is set by the user in the interface via the control register (mb_if)

  • asim_common_lib

memory bus interface

for communication with user interface.

  • asim_common_lib
  • 2008 by yngve (auto)