Busy Box and related
- 1 Overview
- 2 BusyBox Hardware tests at UiB
- 3 BusyBox Firmware
- 4 Related documents for BusyBox
ALICE is one of four large detectors situated at the collision points in the Large Hadron Collider (LHC) at CERN. The BusyBox is used by four of ALICE’s sub-detectors: Time Projection Chamber (TPC), Photon Spectrometer (PHOS), Forward Multiplicity Detector (FMD) and Electromagnetic Calorimeter (EMCal)
Triggers initiate data readout from ALICE’s sub-detectors and are received by the DCS board via an optical cable interface. The triggers and associated data are routed from the TTCrx ASIC on the DCS board to the BusyBox FPGA(s). Here, the L1a and Serial B line raw data is decoded by the Trigger Receiver firmware module.
Every time a trigger sequence starts the Fee starts buffering data, i.e. a buffer in the Fee is used. A valid trigger sequence ends with an L2a trigger and the event data along with the event ID is sent to the D-RORCs.
The purpose of BusyBox is to let the Central Trigger Processor (CTP) know when the Fee’s buffers are full by asserting a busy signal which prevents further issuing of triggers. The BusyBox and D-RORCs receives a unique event ID from the Fee after an event. After a valid trigger sequence ends the BusyBox will ask the D-RORCs if they have received the same event ID as the BusyBox did. If they do not reply with the same ID it means data has not been shipped from the Fee to the D-RORC, hence, the buffer in the Fee still holds event data.
The Fee buffers can hold 4 or 8 events and the BusyBox keeps track of free buffers. The busy is asserted if the buffers are full.
Interaction with the BusyBox is done through the DCS board, either via Ethernet or UART.
The BusyBoxes are located in the DAQ counting rom.
BusyBox Hardware tests at UiB
In one of our labs at UiB we have a setup for testing new BusyBox firmware in hardware before releasing it. The setup features a full readout chain for one channel of the ALICE TPC.
Components in LAB setup :
- Local Trigger Crate (LTU)
- Readout Control Unit (RCU) with Front End Cards (FEC)
- Local Data Concentrator (LDC) with 3 DAQ ReadOut Receiver Cards (DRORC) and date software.
- BusyBox with 2 FPGAs but only 1U rack.
Source Code Repositories
Compiled BusyBox Firmware Versions
There are two versions of the BusyBox. One with two FPGAs and the other with only one FPGA. If only one FPGA is present it should be programmed with 'busybox_fpga1_solo.bit'. If two FPGAs are present then use 'busybox_fpga1.bit' and 'busybox_fpga2.bit'. Alternatively fpga2 can be prgrammed with 'dummy.bit'.
- Revision 31
DCS board firmware for BusyBox
Generating FPGA configuration files from source code
- Check out the desired revision from the SVN repository.
- Navigate to .../busybox_firmware/trunk/ISE_projects
- Run the TCL script named bbiseproject.tcl with Xilinx' TCL interpreter. The script takes three commandline arguments :
- fpga_version - see BusyBox FPGAs
- source_dir - where the source code is located. Including constraints and cores.
- project_dir - location where project is created. Note folder has to exist and should not already contain an ISE project.
D:\busybox_firmware\trunk\ISE_projects>xtclsh bbiseproject.tcl busybox_fpga1_solo ..\source test
- Generate the cores with CoreGen (If it not already done)
- This can be done by using the CoreGen GUI or by invoking coregen in batch mode from the commandline. To use the GUI; start coregen while in .../busybox_firmware/trunk/source/cores.
- For batch mode : .../busybox_firmware/trunk/source/cores/coregen -b 'core'.xco replace 'core' with real name for all *.xco-files.
- Open the project with ISE Project Navigator.
- Run process 'Generate Programming File'