Difference between revisions of "Busy Box and related/BusyBox Registers"

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m (Created page with '{| border="1" cellpadding="1" cellspacing="0" |colspan="5"| ====Busy Box Status and Contol Registers==== |- !Address !Read/Write !Name !Description !Default Value |- |0x0001 |RW ...')
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Revision as of 17:02, 20 October 2009

Busy Box Status and Contol Registers

Address Read/Write Name Description Default Value
0x0001 RW TX module For sending messages to DRORCs. Bit 7-0 is TX data. Bit 15-8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels. TBD
0x1XXX RW RX memory Memory where all messages received from DRORCs will be stored. TBD
0x2000 R RX memory pointer Holds the value where the next message will be written in RX memory. TBD
0x2001 R EventID count Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. TBD
0x2002 R Current EventID(35-32) The EventID which is currently being matched. TBD
0x2003 R Current EventID(31-16) TBD
0x2004 R Current EventID(15- 0) TBD
0x2005 R Newest EventID(35-32) The EventID most recently received from the TTC system. TBD
0x2006 R Newest EventID(31-16) TBD
0x2007 R Newest EventID(15- 0) TBD
0x2008 RW L0 trigger timeout Number of clock cycles 'busy' will be asserted after an L0 trigger. Note: The busy will not be deasserted if the buffers are full. TBD
0x2009 RW FEE buffers available Config: Holds the number buffers assumed on the FEE. TBD
0x200A RW Halt FW matching If LSB is set to 1 the internal FSM will halt in a wait state. TBD
0x200B w Force match Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. TBD
0x200C RW Re-Request Timeout Number of clock cycles to wait in between sending requests to the DRORCs. TBD
0x200D R Current RequestID Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. TBD
0x200E R Retry Count Number of times requests have been sent to DRORCs. TBD
0x2010 R Busy time(31-16) Holds value of counter for number of clock TBD
0x2011 R Busy time(15- 0) cycles BUSY has been asserted. TBD
0x2012 RW RX mem filter Allows filtering of messages that are stored in RX memory. Bit 7-0 is the pattern that will be matched with the channelnumber of the message. Bit 15-8 allows enableing matching of individual bits 7-0. TBD
0x21XX RW Channel Registers 'XX' in the address gives the channelnumber in hexadecimal. Bit 0 is enable/disable (0/1) Bit 1 indicates that the current EventID has been matched on this channel. TBD