Busy Box and related/BusyBox Registers

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Busy Box Status and Control Registers
Name Address Mode Description Default Value
TX module(15:0) 0x0001 RW For sending messages to DRORCs.
  • Bit 7:0 is TX data.
  • Bit 15:8 gives channelnumber in hexadecimal. Any value greater than the actual number of channels will result in a broadcast on all channels.
 0x0000
RX memory 0x1000-0x1FFF RW Memory where all messages received from DRORCs will be stored. One message is stored over 4 addresses:
  • Address ending "00" - 0x0 & RequestID(3:0) & OrbitID(23:16)
  • Address ending "01" - OrbitID(15:0)
  • Address ending "10" - 0x0 BunchCountID(11:0)
  • Address ending "11" - DRORCID(7:0) & ChannelNumber(7:0)
 0x0000
RX memory pointer(13:0) 0x2000 R Holds the value where the next message will be written in RX memory. The RX memory pointer will increase by 4 for each message. 0x0000
EventID FIFO count(3:0) 0x2001 R Number of eventIDs stored in the FIFO, excluding the eventID currently being matched, if any. 0x0000
Current EventID(35:32) 0x2002 R The EventID which is currently being matched. 0x0000
Current EventID(31:16) 0x2003 R 0x0000
Current EventID(15:0) 0x2004 R 0x0000
Newest EventID(35:32) 0x2005 R The EventID most recently received from the Trigger system. 0x0000
Newest EventID(31:16) 0x2006 R 0x0000
Newest EventID(15:0) 0x2007 R 0x0000
L1 Trigger Timeout(15:0) 0x2008 RW Time in 10 us resolution the 'busy' will be asserted after an L1A trigger. Note: The busy will not be deasserted if the buffers are full. 0x000A
Busy Condition(15:0) 0x2009 RW Status and control registers concerning the BUSY generation
  • Bit 15 - Busy because TTCrx_ready is low.
  • Bit 14 - Busy because MEB count >= MEB limit
  • Bit 13 - Busy because L1 timeout is active.
  • Bit 12 - Busy because Trigger Receiver Module is busy receiving a sequence.
  • Bit 11 - Busy because the maximum Trigger Burst length has been exceeded.
  • Bit 10 - Busy because two buffers are, or have been used, in new sparse mode
  • Bit 9:8 - Unused
  • Bit 7:4 - Current MEB count.
  • Bit 3:0 - MEB Limit: Limit for the maximum number of MEBs to count before busy will be asserted.
 0x0000
Halt FSM matching(0) 0x200A RW If LSB is set to 1 the internal State Machine (FSM) will halt in a wait state and will stop requesting EventIDs from the DRORCs. 0x0001
Force match(0) 0x200B T Writing 0x1 when FSM halt is set, will force the FSM to move on to the next EventID even if it is not matched. Note : FSM must be halted before this has any effect. N/A
Re-Request Timeout(15:0) 0x200C RW Number of clock cycles (25 ns) to wait in between sending requests to the DRORCs. 0x07FF
Current RequestID(3:0) 0x200D R Holds the RequestID the BusyBox is using to request eventIDs from the DRORCs. 0x0000
Retry Count(15:0) 0x200E R Number of times the FSM has sent requests to DRORCs. Will reset to 0 for start of every eventID. 0x0000
Busy time(31:16) 0x2010 R Holds value of counter for number of clock cycles BUSY has been asserted. 0x0000
Busy time(15:0) 0x2011 R 0x0000
RX mem filter(15:0) 0x2012 RW Allows filtering of messages that are stored in RX memory.
  • Bit 7:0 is the pattern that will be matched with the channelnumber of the message.
  • Bit 15:8 allows enableing matching of individual bits 7-0.
 0x0000
Number of Channels 0x2014 R Number of channels (in hexadecimal) the firmware includes. This is a generic set at compile-time. N/A
Firmware Revision 0x2015 R Firmware revision in hexadecimal. Holds the revision number of the source in SVN that this FW was compiled from. Current : 54 0x0036
Stresstest Enable(0) 0x2016 RW Duplicates input on channel 0 to all other channels. Used for testing the device with all channels enabled when only one physical DRORC is available. 0x0000
Burst Size(5:0) 0x2017 RW The maximum burst size. A value of 0 disables the Burst Interlock feature. Maximum value is 63. 0x0000
Burst Interlock Leak Time(15:0) 0x2018 RW Leak time for the Burst Interlock "leaky bucket" defined in steps of 10 us. Maximum leak time is 655.4 ms. 0x0000
Trigger Mode(2:0) 0x2019 RW Control registers concerning the BUSY/trigger mode
  • Bit 2 - Not used
  • Bit 1 - New sparse mode enabled
  • Bit 0 - Not used
 0x0000
Current Trigger Event Info(12:0) 0x2050 R Holds the Event Info for current eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Current Trigger Event Error(24:16) 0x2051 R Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Current Trigger Event Error(15:0) 0x2052 R Holds the Event Error for current eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Newest Trigger Event Info(12:0) 0x2054 R Holds the Event Info for newest eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Newest Trigger Event Error(24:16) 0x2055 R Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Newest Trigger Event Error(15:0) 0x2056 R Holds the Event Error for newest eventID as reported by the TRM. See TRM registers for bitmapping. 0x0000
Channel Registers 0x21XX RW 'XX' in the address gives the channelnumber in hexadecimal.
  • Bit 0 is enable(1)/disable(0)
  • Bit 1 indicates that the current EventID has been matched on this channel.
 0x0001


Trigger Receiver Module Status and Control Registers
Name Address Type Description

Control[23:0]

0x3000

RW

[0] Serial B channel on/off Default: 1

[1] Disable_error_masking 0

[2] NA 0

[3] L0 support 1

[4:7] (Not Used)

[8] L2a FIFO storage mask 1

[9] L2r FIFO storage mask 1

[10] L2 Timeout FIFO storage mask 1

[11] L1a message mask 1

[12] Trigger Input Mask Enable 0

[13:15] (Not Used)

[16] Bunch_counter overflow -

[17] Run Active -

[18] Busy (receiving sequence) -

[19] Not Used

[23:20] CDH version 0x2

Module Reset

0x3001

T

Reset Module

NA

0x3002

NA

0x3003

Reset Counters

0x3004

T

Write to this registers will reset the counters in the module

Issue Testmode

0x3005

T

Debug: Issues testmode sequence. Note that serialB channel input MUST be disabled when using this feature.

L1_Latency[15:0]

0x3006

RW

[15:12] Uncertainty region +- N. default value 0x2 (50 ns)

[11:0] Latency from L0 to L1, default value 0x0D4 (5.3 us)

L2_Latency[31:0]

0x3007

RW

[15:0] Max Latency from BC0 to L2, default value 0x4E20 (500 us)

[31:16] Min Latency from BC0 to L2, default value 0x0C80 (80 us)

L2_Extdended

Latency[31:0]

0x3009

RW

[15:0] Max Latency from BC0 to L2 Extended window end, default value 0x4E48 (501 us)

[31:16] Min Latency from BC0 to L2 Extended window start, default value 0x0C80 (80 us)

L1_msg_latency[31:0]

0x300A

RW

[15:0] Max Latency from BC0 to L1 msg, default value 0x0028 (1 us)

[31:16] Min Latency from BC0 to L1 msg, default value 0x0F8 (6,2 us)

Pre_pulse_counter

[15:0]

0x300B

R

Number of decoded pre-pulses.

BCID_Local

[11:0]

0x300C

R

Number of bunchcrossings at arrival of L1 trigger.

L0_counter[15:0]

0x300D

R

Number of L0 triggers

L1_counter[15:0]

0x300E

R

Number of L1 triggers

L1_msg_counter[15:0]

0x300F

R

Number of successfully decoded L1 messages

L2a_counter[15:0]

0x3010

R

Number of successfully decoded L2a messages

L2r_counter[15:0]

0x3011

R

Number of successfully decoded L2r messages

NA

0x3012

Bunchcounter

[11:0]

0x3013

R

Debug: Number of bunchcrossings

hammingErrorCnt

[31:0]

0x3016

R

[15:0] Number of single bit hamming errors [31:16] Number of double bit hamming errors

ErrorCnt

[31:0]

0x3017

R

[15:0] Number of message decoding errors

[31:16] Number of errors related to sequence and timeouts.

Buffered_events

[4:0]

0x3020

R

Number of events stored in the FIFO.

DAQ_Header01[31:0]

0x3021

R

Latest received DAQ Header 1

DAQ_Header02[31:0]

0x3022

R

Latest received DAQ Header 2

DAQ_Header03[31:0]

0x3023

R

Latest received DAQ Header 3

DAQ_Header04[31:0]

0x3024

R

Latest received DAQ Header 4

DAQ_Header05[31:0]

0x3025

R

Latest received DAQ Header 5

DAQ_Header06[31:0]

0x3026

R

Latest received DAQ Header 6

DAQ_Header07[31:0]

0x3027

R

Latest received DAQ Header 7

Event_info

[17:0]

0x3028

R

Latest Received Event information:

[0] ‘0’

[1] Region of Interest announced (=ESR)

[2] ‘0’

[3] ‘0’

[4:7] Calibration/SW trigger type (= RoC)

[8] Software trigger event

[9] Calibration trigger event

[10] Event has L2 Reject trigger

[11] Event has L2 Accept trigger

[12] Include payload

[17:13] SCLK phase when (L0/L1)trigger arrives

Event_error

[24:0]

0x3029

R

Latest Received Event error conditions:

[0] Serial B Stop Bit Error

[1] Single Bit Hamming Error Individually Addr.

[2] Double Bit Hamming Error Individually Addr.

[3] Single Bit Hamming Error Broadcast.

[4] Double Bit Hamming Error Broadcast.

[5] Unknown Message Address Received

[6] Incomplete L1 Message

[7] Incomplete L2a Message

[8] NA

[9] TTCrx Address Error (not X”0003”)

[10] Spurious L0

[11] Missing L0

[12] Spurious L1

[13] Boundary L1

[14] Missing L1

[15] L1 message arrives outside legal timeslot

[16] L1 message missing/timeout

[17] L2 message arrives outside legal timeslot

[18] L2 message missing/timeout

[19] Boundary L2 Message

[20] NA

[21] Prepulse error (=0; possible future use)

[22] L1 message content error

[23] L2 message content error

[24] NA

L1_MessageHeader[11:0]

0x3030

R

Debug: Latest received L1 Message

L1_MessageData1[11:0]

0x3031

R

Debug: Latest received L1 Message

L1_MessageData2[11:0]

0x3032

R

Debug: Latest received L1 Message

L1_MessageData3[11:0]

0x3033

R

Debug: Latest received L1 Message

L1_MessageData4[11:0]

0x3034

R

Debug: Latest received L1 Message

L2aMessageHeader[11:0]

0x3035

R

Debug: Latest received L2a Message

L2aMessageData1[11:0]

0x3036

R

Debug: Latest received L2a Message

L2aMessageData2[11:0]

0x3037

R

Debug: Latest received L2a Message

L2aMessageData3[11:0]

0x3038

R

Debug: Latest received L2a Message

L2aMessageData4[11:0]

0x3039

R

Debug: Latest received L2a Message

L2aMessageData5[11:0]

0x303A

R

Debug: Latest received L2a Message

L2aMessageData6[11:0]

0x303B

R

Debug: Latest received L2a Message

L2aMessageData7[11:0]

0x303C

R

Debug: Latest received L2a Message

L2rMessageHeader[11:0]

0x303D

R

Debug: Latest received L2r Message

RoIMessageHeader

[11:0]

0x303E

R

Debug: Latest received RoI Message

RoIMessageData1[11:0]

0x303F

R

Debug: Latest received RoI Message

RoIMessageData2[11:0]

0x3040

R

Debug: Latest received RoI Message

RoIMessageData3[11:0]

0x3041

R

Debug: Latest received RoI Message

FIFO_read_enable

0x3080

T

Debug: Triggers a readout pulse to FIFO

FIFO_DAQHeader

[31:0]

0x3081

R

Debug: Output of FIFO

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