List of included modules in hierachical order:
Detector module interface (dm_if)
interface to readout electroncs for the detector modules. Reads
energy, pixel and ASIC address, in addition to multihit information. Also
controls the pipelined ADC.
MUX (scdp_ch_mux)
FIFO
DPU interface (dpu_if)
xlink_rx
rx register
xlink_tx
tx register
tx control fsm
Address decoder (adrdec_bgo)
Binning control module (BCM) (bin_ctrl_module)
Scdp channel mux
Bin address generator
Bin access control
Swing buffer
Bin module address arbiter
Memory bus interface (mb_if)
RCU master (rcumaster)
LED control
Memory bus interface (mb_if)
XA config (xa_cfg)
Resync register
Clock reset (clkrst)
Timetag generation (tt_gen)
