Revision as of 20:50, 18 October 2010 by Ako054 (talk | contribs) (DPU interface (dpu_if))

List of included modules in hierachical order:

Detector module interface (dm_if)

interface to readout electroncs for the detector modules. Reads energy, pixel and ASIC address, in addition to multihit information. Also controls the pipelined ADC.

Offset substract

Finds and subtracts the offset from ADC data, ensuring a consistent mean value of zero between all four detector chains

Hit discriminator (hit_dicr)

determines whether there was an event or not?

Memory bus interface (mb_if)

for communication with user interface. including a control register and a fsm. basically a translator, translating memory data into commands for active module and delivers status reports.


  • memory address memadr_in (from adress decoder)
  • memory data memdat_in (from address decoder, incl. command )
  • status register sr[0-3] (from logic module, e.g. tmon)
  • clk etc.


  • memdat_out (to address decoder, incl. answer)
  • control registers cr[0-3] (to logig module, incl. command)

MUX (scdp_ch_mux)


DPU interface (dpu_if)

is interfacing the DPU emulator, input: commands, output: data, status

  • asim_common_lib
 port (
    clk               : in  std_logic;  -- clock
    arst_n            : in  std_logic;  -- asynchronous reset    
    memdat_in         : in  std_logic_vector(7 downto 0);  -- memory bus data input
    serial_data_in    : in  std_logic;  -- serial data input
    serial_strobe_in  : in  std_logic;  -- serial strobe input
    serial_data_out   : out std_logic;  -- serial data output
    serial_strobe_out : out std_logic;  -- serial strobe output
    RnW               : out std_logic;  -- read / write control
    ld_memdat         : out std_logic;  -- load memory data
    memadr_out        : out std_logic_vector(13 downto 0);  -- memory address
    memdat_out        : out std_logic_vector(7 downto 0);   -- memory data
    scdp              : in  std_logic_vector(47 downto 0);  -- scdp input
    enable            : in  std_logic;  -- enable input from DPU
    fifo_empty        : in  std_logic;  -- fifo empty indicator
    fifo_read         : out std_logic;  -- fifo read enable
    fifo_full         : in  std_logic := '0');  -- fifo full indicator



Description: receiver for "xlink", a serial data strobe encoded point to -- point communications protocol for the ASIM MXGS

rx register

reception register for DPU interface




tx register

transmission register for DPU interface

tx control fsm

Address decoder (adrdec_bgo)

Binning control module (BCM) (bin_ctrl_module)

Scdp channel mux

Bin address generator

Bin access control

Swing buffer

Bin module address arbiter

Memory bus interface (mb_if)

RCU master (rcumaster)

LED control

Memory bus interface (mb_if)

XA config (xa_cfg)

XA register verification (xa_reg_verify)

FSM, ASIC configuration register verifier

RAM (dpram1k8)

RAM to memorize control register, dual port RAM for volatile XA configuration data

Memory bus interface



Resync register

Clock reset (clkrst)

Timetag generation (tt_gen)