Difference between revisions of "Cadence Virtuoso overview"

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=Analog IC design flow using Cadence from basics (Schematic capture, Netlist extraction, Simulating using ELDO, Layout, Signoff Layout)=
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= IC design flow using Cadence =
  
[[ TSMC 130nm process ]]
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We have access to several silicon technologies from different foundries
  
[[ IHP 130nm process ]]
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* 130nm CMOS process from Taiwan Semiconductor Manufacturing: '''[[ TSMC 130nm process ]]'''
 
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* 130nm SiGe process from Innovations for High Performance Microelectronics: '''[[ IHP 130nm process ]]'''
[[ AMS 350nm process ]]
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* 350nm  CMOS process from Austria Mikro Systeme: '''[[ AMS 350nm process ]]'''
  
 
= Simulation =
 
= Simulation =

Revision as of 12:37, 18 October 2017

IC design flow using Cadence

We have access to several silicon technologies from different foundries

Simulation

Virtuoso Testbench

Layout

Layout XL and IHP SG13S

Helpful stuff

MikroserverSetup - setup for easy connection to the mikroservers and Cadence Virtuoso

Transistor operating point printer - Script to extract transistor operating point parameters after simulation.

ADEXL-butterfly-curves - Howto make DC butterfly curves easily.