Difference between revisions of "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"

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Tested on Xilinx Vivado 2017.3.
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[[File:Example.jpg|thumbnail]]Tested on Xilinx Vivado 2017.3.
  
  
Start Vivado
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Start ./vivado from installed directory.
Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. [[File:New_project_name.png|thumbnail|center]]
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Goto: ''File -> New Project -> Next''. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next. [[File:New_project_name.png|thumbnail|center]]
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Do not add any sources, but make sure that both Target and Simulator Language is set to the appropriate language you're using. In this project we will use VHDL. Click Next.
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Here you must provide a constraints file named "ZYBO_Master.xdc", available from [https://github.com/Digilent/digilent-xdc/ GitHub].

Revision as of 16:10, 28 November 2017

Tested on Xilinx Vivado 2017.3.


Start ./vivado from installed directory.

Goto: File -> New Project -> Next. For this project we will name it "axi4_lite_tutorial_project" and place it in a folder named tutorials. Click Next and choose RTL Project, then Next.

New project name.png

Do not add any sources, but make sure that both Target and Simulator Language is set to the appropriate language you're using. In this project we will use VHDL. Click Next. Here you must provide a constraints file named "ZYBO_Master.xdc", available from GitHub.