Modelsim/Questa: Difference between revisions
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Mapping av alterabibliotek: | Mapping av alterabibliotek: | ||
<pre> | <pre> | ||
vmap | vmap cyclonev /prog/altera/vhdl_libs/cyclonev | ||
vmap lpm /prog/altera/ | vmap lpm /prog/altera/vhdl_libs/lpm | ||
vmap altera_mf /prog/altera/ | vmap altera /prog/altera/vhdl_libs/altera | ||
vmap altera_mf /prog/altera/vhdl_libs/altera_mf | |||
</pre> | </pre> | ||
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[[Simulering av VHDL]] | [[Simulering av VHDL]] | ||
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[[Synthese av VHDL]] | [[Synthese av VHDL]] | ||
[[Synthese av VHDL - Oppdatert]] | |||
== Referanselitteratur == | == Referanselitteratur == | ||
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL] | |||
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[http://www.ashenden.com.au/ Ashenden Designs] | |||
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[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook] | |||
[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example] | |||
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[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)] | |||
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[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)] | |||
[http://model.com/content/modelsim-pe-simulation-and-debug Modelsim] | |||
[http://m.eet.com/media/1151614/23798-46098.pdf 10 tips for generating reusable VHDL] | |||
[http://www.actel.com/documents/hdlcode_ug.pdf Actel HDL coding Style Guide] | |||
[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer] | |||
[ | [https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ] | ||
[[Category:Mikroelektronikk]] | [[Category:Mikroelektronikk]] |