Modelsim/Questa: Difference between revisions

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<!--
Mapping av alterabibliotek:
<pre>
vmap cyclonev /prog/altera/vhdl_libs/cyclonev
vmap lpm /prog/altera/vhdl_libs/lpm
vmap altera /prog/altera/vhdl_libs/altera
vmap altera_mf /prog/altera/vhdl_libs/altera_mf
</pre>
-->
[[Simulering av VHDL]]
[[Simulering av VHDL]]


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[[Synthese av VHDL]]
[[Synthese av VHDL]]
[[Synthese av VHDL - Oppdatert]]


== Referanselitteratur ==
== Referanselitteratur ==
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]
[http://en.wikipedia.org/wiki/VHDL Wikipedia:VHDL]


<!--
[http://www.ashenden.com.au/ Ashenden Designs]
dead link
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[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]
[http://freerangefactory.org/books_tuts.html Free Range VHDL textbook]


[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]
[http://esd.cs.ucr.edu/labs/tutorial/ VHDL Tutorial: Learn by Example]


<!--
[http://www.ashenden.com.au/designers-guide/VHDL-quick-start.pdf VHDL Quick Start (slides by Ashenden)]
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[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]
[http://www.ioenotes.edu.np/media/notes/embedded-system/vhdl.pdf VHDL Quick Start (slides by Ashenden)]


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[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]
[http://www.seas.upenn.edu/~ese171/vhdl/vhdl_primer.html VHDL primer]


[http://bitvis.no/products/bitvis-utility-library/ Bitvis utility library]
[https://bitvis.no/dev-tools/uvvm/ Bitvis Universal VHDL Verification Methodology ]
 
[https://github.com/UVVM Bitvis UVVM på GitHub ]


[[Category:Mikroelektronikk]]
[[Category:Mikroelektronikk]]

Latest revision as of 21:13, 4 February 2021