User contributions for Nfyku
13 February 2024
- 12:1412:14, 13 February 2024 diff hist +79 m Bitvis UVVM VHDL Verification Component Framework →Simulation current
24 January 2024
- 07:5807:58, 24 January 2024 diff hist +126 m Synthese av VHDL →Precision current
- 07:5407:54, 24 January 2024 diff hist +104 m Simulering av VHDL →Starte Questa Sim current
5 February 2021
- 13:4413:44, 5 February 2021 diff hist +13 m Synthese av VHDL oppdatert sdf-inkludering med sdfnoerror
- 12:1012:10, 5 February 2021 diff hist +278 m Synthese av VHDL →Koden til alu_tb.vhdl
- 08:0508:05, 5 February 2021 diff hist 0 m Synthese av VHDL →Precision
4 February 2021
- 21:1321:13, 4 February 2021 diff hist −16 m Modelsim/Questa →Referanselitteratur current
- 21:0921:09, 4 February 2021 diff hist +2 m VHDL Testbenk →Do-file og testbenk current
- 21:0821:08, 4 February 2021 diff hist −14 m VHDL Testbenk No edit summary
- 21:0621:06, 4 February 2021 diff hist +13 m Simulering av VHDL →Starte Questa Sim
- 21:0521:05, 4 February 2021 diff hist +1 m Synthese av VHDL No edit summary
- 21:0221:02, 4 February 2021 diff hist −383 Modelsim/Questa No edit summary
- 13:4813:48, 4 February 2021 diff hist +4 m Synthese av VHDL No edit summary
- 13:4613:46, 4 February 2021 diff hist +2 m Synthese av VHDL →Precision
- 13:3913:39, 4 February 2021 diff hist −20 m Synthese av VHDL No edit summary
- 13:3713:37, 4 February 2021 diff hist −165 m Synthese av VHDL No edit summary
- 12:5212:52, 4 February 2021 diff hist +496 Synthese av VHDL Updated to Vivado
15 October 2020
- 11:3011:30, 15 October 2020 diff hist +3 m IHP 130nm process No edit summary
- 09:2009:20, 15 October 2020 diff hist +220 m IHP 130nm process No edit summary
- 09:1909:19, 15 October 2020 diff hist −2 m Layout XL and IHP SG13S No edit summary
- 08:3208:32, 15 October 2020 diff hist +26 m IHP 130nm process No edit summary
- 08:0708:07, 15 October 2020 diff hist 0 m Layout XL and IHP SG13S No edit summary
- 07:5807:58, 15 October 2020 diff hist −1 m IHP 130nm process Updated to new software distro and design kit
23 September 2020
- 11:3911:39, 23 September 2020 diff hist +506 m Symbolsk løsning av nodeligninger med Matlab Added calculation for all capacitors current
- 11:1311:13, 23 September 2020 diff hist −5 m Symbolsk løsning av nodeligninger med Matlab No edit summary
- 11:0211:02, 23 September 2020 diff hist −35 m Symbolsk løsning av nodeligninger med Matlab Updated for newer Matalb versions (tested on R2020b)
7 September 2020
- 13:3713:37, 7 September 2020 diff hist +113 m PHYS222 →Prosessteknologi current
- 13:3313:33, 7 September 2020 diff hist +79 m PHYS222 →Prosessteknologi
- 13:2613:26, 7 September 2020 diff hist +63 m PHYS222 →Prosessteknologi
18 August 2020
- 14:1114:11, 18 August 2020 diff hist +66 m Microelectronics group No edit summary current
- 14:0714:07, 18 August 2020 diff hist +119 m Microelectronics group No edit summary
30 March 2020
- 08:2108:21, 30 March 2020 diff hist +35 m SSH tunnel No edit summary current
- 08:1008:10, 30 March 2020 diff hist −25 m IHP 130nm process No edit summary
- 07:5407:54, 30 March 2020 diff hist −227 m MikroserverSetup Removed full path references
2 March 2020
- 14:5414:54, 2 March 2020 diff hist −132 m PHYS321 →Nettressurser current
- 14:4514:45, 2 March 2020 diff hist +97 m PHYS222 →Prosessteknologi
- 14:4114:41, 2 March 2020 diff hist +95 m PHYS222 →Prosessteknologi
31 January 2020
- 12:5412:54, 31 January 2020 diff hist +5 m VHDL Testbenk →Do-file og testbenk
- 12:5312:53, 31 January 2020 diff hist +58 m VHDL Testbenk →Do-file og testbenk
- 12:5112:51, 31 January 2020 diff hist 0 m Simulering av VHDL →Starte Questa Sim
30 January 2020
- 15:1915:19, 30 January 2020 diff hist +5 m Synthese av VHDL →Modelsim
- 13:5913:59, 30 January 2020 diff hist +30 m Simulering av VHDL →Signaler og variable
- 13:5713:57, 30 January 2020 diff hist +141 m Simulering av VHDL →Signaler og variable
4 November 2019
- 14:5114:51, 4 November 2019 diff hist −5 m MikroserverSetup No edit summary
- 10:1810:18, 4 November 2019 diff hist −5 m IHP 130nm process No edit summary
- 09:0109:01, 4 November 2019 diff hist 0 m IHP 130nm process No edit summary
- 09:0109:01, 4 November 2019 diff hist 0 m IHP 130nm process No edit summary
23 January 2019
- 13:0613:06, 23 January 2019 diff hist +9 m Modelsim/Questa Oppdatert til bitvis UVVM
30 October 2018
- 12:0712:07, 30 October 2018 diff hist +7 m Gitlab Changed from gitlab to git.app current
13 September 2018
- 09:1009:10, 13 September 2018 diff hist −17 m PHYS222 No edit summary