User contributions for Yag005
2 March 2019
- 16:5216:52, 2 March 2019 diff hist +380 m User:Yag005 Updated information and added link to thesis current
9 January 2018
- 13:5813:58, 9 January 2018 diff hist +34 m Running FreeRTOS on Xilinx Zybo No edit summary current
4 January 2018
- 15:1915:19, 4 January 2018 diff hist +14 Running concurrent application projects in Xilinx SDK No edit summary current
- 15:1915:19, 4 January 2018 diff hist +1,928 N Running concurrent application projects in Xilinx SDK Created page with "Tested on Xilinx SDK 2017.4, with Xilinx Digilent Zybo SoC. = Running concurrent application projects in Xilinx SDK = This tutorial gives a brief introduction to running conc..."
- 15:1715:17, 4 January 2018 diff hist +27 N File:Running concurrent xilinx sdk added.png File uploaded with MsUpload current
- 15:0815:08, 4 January 2018 diff hist +27 N File:Running concurrent xilinx sdk not added.png File uploaded with MsUpload current
- 14:3214:32, 4 January 2018 diff hist +57 N Xilinx SDK Created page with "Running concurrent application projects in Xilinx SDK" current
- 14:3114:31, 4 January 2018 diff hist +71 N Xilinx Vivado Created page with "Creating example project with AXI4 Lite peripheral in Xilinx Vivado" current
- 14:3014:30, 4 January 2018 diff hist +42 m Microelectronics group No edit summary
- 14:2714:27, 4 January 2018 diff hist +59 m Microelectronics group Added Xilinx to comply with readability criteria.
6 December 2017
- 18:2318:23, 6 December 2017 diff hist +9 FreeRTOS FSBL No edit summary current
- 18:2218:22, 6 December 2017 diff hist +1,449 FreeRTOS FSBL No edit summary
- 17:5317:53, 6 December 2017 diff hist −9 m FreeRTOS FSBL No edit summary
- 17:5317:53, 6 December 2017 diff hist +27 N File:Fsbl created.png File uploaded with MsUpload current
- 17:4917:49, 6 December 2017 diff hist +27 N File:Project explorer start.png File uploaded with MsUpload current
- 17:4417:44, 6 December 2017 diff hist +1,005 Running FreeRTOS on Xilinx Zybo No edit summary
- 17:3517:35, 6 December 2017 diff hist +27 N File:Main code.png File uploaded with MsUpload current
- 17:3217:32, 6 December 2017 diff hist +27 N File:AXILedBlink code.png File uploaded with MsUpload current
- 17:2617:26, 6 December 2017 diff hist +405 m Running FreeRTOS on Xilinx Zybo No edit summary
- 17:2417:24, 6 December 2017 diff hist +27 N File:Remove include demo libs.png File uploaded with MsUpload current
- 17:0517:05, 6 December 2017 diff hist 0 File:Source folder.png Yag005 uploaded a new version of File:Source folder.png current
- 17:0117:01, 6 December 2017 diff hist +34 m Running FreeRTOS on Xilinx Zybo No edit summary
- 16:0416:04, 6 December 2017 diff hist 0 File:Source folder.png Yag005 uploaded a new version of File:Source folder.png
- 16:0016:00, 6 December 2017 diff hist +135 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:5315:53, 6 December 2017 diff hist 0 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:5215:52, 6 December 2017 diff hist +24 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:5115:51, 6 December 2017 diff hist +492 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:5115:51, 6 December 2017 diff hist +27 N File:FreeRTOSConfig cpu freq edit.png File uploaded with MsUpload current
- 15:4615:46, 6 December 2017 diff hist +27 N File:Port c edit.png File uploaded with MsUpload current
- 15:3915:39, 6 December 2017 diff hist +27 N File:Lscript id edit.png File uploaded with MsUpload current
- 15:2315:23, 6 December 2017 diff hist +139 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:2315:23, 6 December 2017 diff hist +27 N File:Source folder.png File uploaded with MsUpload
- 15:1915:19, 6 December 2017 diff hist +54 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:1615:16, 6 December 2017 diff hist −28 Running FreeRTOS on Xilinx Zybo No edit summary
- 15:1115:11, 6 December 2017 diff hist −4 m Running FreeRTOS on Xilinx Zybo No edit summary
- 15:0315:03, 6 December 2017 diff hist +256 Running FreeRTOS on Xilinx Zybo No edit summary
- 14:5814:58, 6 December 2017 diff hist +978 Running FreeRTOS on Xilinx Zybo No edit summary
- 13:2913:29, 6 December 2017 diff hist +28 m Microelectronics group No edit summary
- 13:2613:26, 6 December 2017 diff hist +549 m Running FreeRTOS on Xilinx Zybo No edit summary
- 13:2513:25, 6 December 2017 diff hist +171 m Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary current
- 13:2313:23, 6 December 2017 diff hist +259 m Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 12:2512:25, 6 December 2017 diff hist +184 N Running FreeRTOS on Xilinx Zybo Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-..."
- 12:2512:25, 6 December 2017 diff hist −36 m FreeRTOS FSBL No edit summary
- 12:2312:23, 6 December 2017 diff hist +6 m FreeRTOS No edit summary current
- 12:2312:23, 6 December 2017 diff hist +91 m FreeRTOS No edit summary
4 December 2017
- 18:1118:11, 4 December 2017 diff hist +100 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 17:0217:02, 4 December 2017 diff hist −94 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 17:0117:01, 4 December 2017 diff hist +834 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 16:5216:52, 4 December 2017 diff hist 0 File:Led port success.png Yag005 uploaded a new version of File:Led port success.png current
- 16:5216:52, 4 December 2017 diff hist −492 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 16:4916:49, 4 December 2017 diff hist +1,477 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 16:4916:49, 4 December 2017 diff hist +27 N File:S00 1.png File uploaded with MsUpload current
- 16:4816:48, 4 December 2017 diff hist +27 N File:S00 2.png File uploaded with MsUpload current
- 16:4816:48, 4 December 2017 diff hist +27 N File:Led ip 1.png File uploaded with MsUpload current
- 16:4816:48, 4 December 2017 diff hist +27 N File:Led ip 2.png File uploaded with MsUpload current
- 16:4816:48, 4 December 2017 diff hist +27 N File:Led ip 3.png File uploaded with MsUpload current
- 16:4816:48, 4 December 2017 diff hist +27 N File:Led port success.png File uploaded with MsUpload
- 14:2414:24, 4 December 2017 diff hist 0 File:Diagram axi4lite periph added.png Yag005 uploaded a new version of File:Diagram axi4lite periph added.png current
- 13:4713:47, 4 December 2017 diff hist +27 N File:Diagram axi4lite periph added.png File uploaded with MsUpload
- 13:4413:44, 4 December 2017 diff hist +337 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 13:4413:44, 4 December 2017 diff hist +27 N File:Add interfaces axi4lite.png File uploaded with MsUpload current
28 November 2017
- 15:0215:02, 28 November 2017 diff hist +202 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:4314:43, 28 November 2017 diff hist +2 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:4314:43, 28 November 2017 diff hist +120 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:4314:43, 28 November 2017 diff hist 0 File:First block.png Yag005 uploaded a new version of File:First block.png current
- 14:3814:38, 28 November 2017 diff hist −2 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:3814:38, 28 November 2017 diff hist +2 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:3714:37, 28 November 2017 diff hist +1 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:3614:36, 28 November 2017 diff hist +429 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:3614:36, 28 November 2017 diff hist +27 N File:First block.png File uploaded with MsUpload
- 14:3314:33, 28 November 2017 diff hist +27 N File:Create block design.png File uploaded with MsUpload current
- 14:2814:28, 28 November 2017 diff hist +425 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:2514:25, 28 November 2017 diff hist +27 N File:New project default part.png File uploaded with MsUpload current
- 14:1014:10, 28 November 2017 diff hist +412 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:0214:02, 28 November 2017 diff hist 0 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:0114:01, 28 November 2017 diff hist 0 File:New project name.png Yag005 uploaded a new version of File:New project name.png current
- 14:0014:00, 28 November 2017 diff hist +43 Creating example project with AXI4 Lite peripheral in Xilinx Vivado No edit summary
- 14:0014:00, 28 November 2017 diff hist 0 File:New project name.png Yag005 uploaded a new version of File:New project name.png
- 13:5713:57, 28 November 2017 diff hist +193 N Creating example project with AXI4 Lite peripheral in Xilinx Vivado Created page with "Tested on Xilinx Vivado 2017.3. Start Vivado Goto: ''File -> New Project -> Next''. For this project we will name it axi4_lite_tutorial_project. File:new_project_name.png|..."
- 13:5713:57, 28 November 2017 diff hist 0 File:New project name.png Yag005 uploaded a new version of File:New project name.png
- 13:5413:54, 28 November 2017 diff hist +27 N File:New project name.png File uploaded with MsUpload
- 13:5013:50, 28 November 2017 diff hist +82 FreeRTOS FSBL No edit summary
- 13:4613:46, 28 November 2017 diff hist +4 FreeRTOS FSBL No edit summary
- 13:4613:46, 28 November 2017 diff hist +47 FreeRTOS FSBL No edit summary
- 13:4613:46, 28 November 2017 diff hist +27 N File:Export hardware.png File uploaded with MsUpload current
- 13:4413:44, 28 November 2017 diff hist +7 FreeRTOS FSBL No edit summary
- 13:4213:42, 28 November 2017 diff hist 0 N File:Launch SDK.png No edit summary current
- 13:4213:42, 28 November 2017 diff hist +305 FreeRTOS FSBL No edit summary
- 13:3313:33, 28 November 2017 diff hist +225 N FreeRTOS FSBL Created page with "Tested on Xilinx Vivado/SDK 2017.3, Ubuntu 16.04 LTS. This tutorial assumes you have completed the "Creating example project with AXI4 Lite peripheral in Xilinx Vivado"-t..."
- 13:2313:23, 28 November 2017 diff hist +67 FreeRTOS No edit summary
- 13:2113:21, 28 November 2017 diff hist +9 FreeRTOS No edit summary
- 13:1913:19, 28 November 2017 diff hist +31 N FreeRTOS Created page with "FSBL First Stage Bootloader"
- 13:1713:17, 28 November 2017 diff hist +48 Microelectronics group →Annet
- 13:1513:15, 28 November 2017 diff hist +78 N User:Yag005 Created page with "Master student in microelectronics group. Contact email: yag005@student.uib.no"