Spice deck: Difference between revisions
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* Models | * Models | ||
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.model nmos nmos (level=1 VT0=0.6 KP=200u LAMBDA=0 | .model nmos nmos (level=1 VT0=0.6 KP=200u LAMBDA=0) | ||
* | * | ||
* Setup | * Setup | ||
* | * | ||
.options nomod nopage | *.options nomod nopage | ||
.width OUT=80 | *.width OUT=80 | ||
*.connect GND 0 | *.connect GND 0 | ||
* | * |
Revision as of 10:21, 9 September 2013
LTspice file:Spice file (Rename to spice.asc after downloading)
Common Source gain stage, max gain * Analysis and design of analog integrated circuits * Problem 3.4 * NB ! Model level 1 only - Similar to hand calcualtions * * Voltage * from to volts VDD VDD GND 3 * Transistor * Drain Gate Source Bulk MN1 Out In GND GND nmos W=10u L=1u * Load Resistor and Capacitor * from to ohms RD VDD Out 5k Cl Out GND 0.1p * Voltage source * from to volts VI In GND DC 1.281 AC 1 * * Models * .model nmos nmos (level=1 VT0=0.6 KP=200u LAMBDA=0) * * Setup * *.options nomod nopage *.width OUT=80 *.connect GND 0 * * Simulation and Plots * *.TF V(Out) VI *.OP .ac dec 10 1k 100.0e9 * Amplitude Bode Plot .plot ac vdb(Out) * Phase Bode Plot .plot ac vp(Out) .END