Common Source gain stage, max gain
* Analysis and design of analog integrated circuits
* Problem 3.4
* NB ! Model level 1 only - Similar to hand calcualtions
*
* Voltage
* from to volts
VDD VDD VSS 3
* Transistor
* Drain Gate Source Bulk
MN1 Out In VSS VSS nmos W=10u L=1u
* Load Resistor and Capacitor
* from to ohms
RD VDD Out 5k
Cl Out VSS 0.1p
* Voltage source
* from to volts
VI In VSS DC 1.281 AC 1
*
* Models
*
.model nmos nmos level=1 VT0=0.6 KP=200u LAMBDA=0
*
* Setup
*
.options nomod nopage
.width OUT=80
.connect vss 0
*
* Simulation and Plots
*
*.TF V(Out) VI
*.OP
.ac dec 10 1k 100.0e9
* Amplitude Bode Plot
.plot ac vdb(Out)
* Phase Bode Plot
.plot ac vp(Out)
.END
