Difference between revisions of "VHDL"

(Created page with '==Modeling concept== there are 3 domains of modeling: * function * structure * geometry each provides a basic modeling concept. a module e.g. a register is an '''entity''', it…')
 
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* conditional and repeated execution
 
* conditional and repeated execution
 
* subprogram calls
 
* subprogram calls
 +
 +
'''''behavioral architecture''''': function of an entity is described in an abstract way. e.g.
 +
<pre>
 +
entity srlatch is
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port ( s,r : in  std_logic;
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      q,qb : out std_logic);
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end srlatch;
 +
 +
architecture behave of calc is
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begin
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foo: process
 +
begin
 +
    Q <= S nand QB;
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    QB <= R nand Q; 
 +
end process  foo;
 +
end architecture behave;
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</pre>
 +
 +
'''''structural architecture''''': only interconnecting subsystems
 +
 +
<pre>
 +
entity nand2 is
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port(a,b: in  std logic;
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      q: out std_logic);
 +
end nand2;
 +
 +
architecture basic of nand2 is
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q <= a nand b after 2 ns;
 +
end architecture nand2;
 +
 +
</pre>
 +
 +
<pre>
 +
entity srlatch is
 +
port( s,r: in  std logic;
 +
    q,qb: out std_logic);
 +
end srlatch;
 +
 +
architecture struct of srlatch is
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signal int_en : std:logic;
 +
 +
sq: entity work.nand2(basic)
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port map (
 +
a => s,
 +
b => qb,
 +
q => q);
 +
 +
rq: entity work.nand2(basic)
 +
port map (
 +
a => r,
 +
b => q,
 +
q => qb);
 +
 +
end architecture srlatch
 +
</pre>

Revision as of 17:30, 28 September 2010

Modeling concept

there are 3 domains of modeling:

  • function
  • structure
  • geometry

each provides a basic modeling concept.

a module e.g. a register is an entity, it's inputs ans outputs are called ports. an architecture is the internal implementation of an entity. it describes the behavior of an entity. architectures includes only processes, collection of actions which are executed in sequences.

types of action that can be performed:

  • evaluating expressions
  • assigning variables and values
  • conditional and repeated execution
  • subprogram calls

behavioral architecture: function of an entity is described in an abstract way. e.g.

entity srlatch is
port ( s,r : in  std_logic;
      q,qb : out std_logic);
end srlatch;

architecture behave of calc is
begin
 foo: process
 begin
    Q <= S nand QB;
    QB <= R nand Q;  
 end process  foo;
end architecture behave;

structural architecture: only interconnecting subsystems

entity nand2 is
port(a,b: in  std logic; 
       q: out std_logic);
end nand2;

architecture basic of nand2 is
q <= a nand b after 2 ns;
end architecture nand2;

entity srlatch is
port( s,r: in  std logic; 
     q,qb: out std_logic);
end srlatch;

architecture struct of srlatch is
signal int_en : std:logic;

sq: entity work.nand2(basic)
port map (
a => s,
b => qb,
q => q);

rq: entity work.nand2(basic)
port map (
a => r,
b => q,
q => qb);

end architecture srlatch