VHDL

Revision as of 10:41, 29 September 2010 by Ako054 (talk | contribs)

Modeling concept

there are 3 domains of modeling:

  • function
  • structure
  • geometry

each provides a basic modeling concept.

a module e.g. a register is an entity, it's inputs ans outputs are called ports. an architecture is the internal implementation of an entity. it describes the behavior of an entity. architectures includes only processes, collection of actions which are executed in sequences.

types of action that can be performed:

  • evaluating expressions
  • assigning variables and values
  • conditional and repeated execution
  • subprogram calls

behavioral architecture: function of an entity is described in an abstract way. e.g.

entity srlatch is
port ( s,r : in  std_logic;
      q,qb : out std_logic);
end srlatch;

architecture behave of calc is
begin
 foo: process
 begin
    Q <= S nand QB;
    QB <= R nand Q;  
 end process  foo;
end architecture behave;

structural architecture: only interconnecting subsystems

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity nand2 is
port(
  a,b : in  std_logic;   
  q   : out std_logic);
end nand2;

architecture basic of nand2 is
begin
q <= a nand b after 2 ns;
end basic;
entity srlatch is
port( s,r: in  std logic; 
     q,qb: out std_logic);
end srlatch;

architecture struct of srlatch is
 begin
 sq: entity work.nand2(basic)
 port map (
   a => s,
   b => qb,
   q => q
 );

 rq: entity work.nand2(basic)
 port map (
   a => r,
   b => q,
   q => qb
 );

end architecture struct;

Packages

grouping a collection of related declarations to serve common purpose. seperat design units that can be worked on independently, reused in different parts of design.

the external view is specified in the package declaration, the implementation is defind in the package body.

the package declaration hosts type, constand, subprogram, signal ... declarations which are shared within the model. in the model then you just need to refer to the package:

package yourpackagename is --declaration
 constant foo: std_logic_vector(7 downto 0) := X"01";
 type  foobar is array (foobar2) of somethingelse;
end package yourpackagename;
use yourpackagename.all;

entity yourentityname is
 port (
  fooport    : in work.yourpackagename.foo;
  foobarport : in work.yourpackagename.foobar;
 );
end entity yourentityname;